Integrated circuits (ICs) send signals outside of the IC circuitry using output driver circuits or drivers. Input/output (I/O) drivers present signals to output signal pads, which connect to a pin, the set of pins referred to as the packaging. The pin or packaging connects to a trace or bus. The signal pad displays inherent parasitic resistance, inductance, and capacitance (sometimes referred to as the characteristic package impedance). The characteristic package impedance affects transmission of the output signal from the signal pad (i.e., the IC). The trace in receipt of the output signal displays transmission line characteristics: resistance, capacitance and inductance (sometimes referred to as the characteristic impedance). The characteristic impedance also affects transmission of the output signal from the signal pad.
Maintaining the output impedance of I/Os is extremely important for maintaining signal integrity of the data being transmitted. Various conditions affect signal quality. For example, where the characteristic package impedance at the I/O pad or pin, and the characteristic impedance of the transmission line (i.e., a trace to which the package is connected) are mismatched, signal reflections occur during voltage level switching of (data) signals. The signal reflections result in undesirable signal degradation. Mismatched impedance can occur for any number of reasons. For example, as the manufacturing process, operating temperature, and voltage supply rails vary, the output impedance of the I/O also tends to vary. The problem is acute at switching, where the output impedance response can vary significantly as the output signal (at the pad) transitions between voltage levels.
Calibrated I/O drivers have been developed to overcome fluctuating I/O output impedance at switching. Calibrated I/Os continually adjust the strength of the output driver stage in an attempt to maintain a constant output impedance at switching. Unfortunately, the output impedance is often linear only over a small range of the output voltage, so a calibrated output does not overcome the problem of fluctuating output impedance for the entire voltage switching range. Switching between logical voltage levels, for example, from a low voltage level to a high voltage level, takes a fixed time period. The initial portion of such a fixed time requires a much larger amount of current than the latter portions of this switching period. U.S. Pat. No. 6,268,750 (“the '750 patent”), incorporated by reference, discloses a circuit for flattening the I/O output impedance response at switching, which improved the then-known calibrated I/Os.
The flattening circuit of the '750 patent includes a combination of pull-up PFETs arranged in a pull-up PFET array. The pull-up PFETs are programmatically enabled by a pull-up calibration word pu_n [5:0], and a pull_up signal to drive an I/O output pad high. The flattening circuit also includes a combination of pull-down NFETs arranged in a pull-down NFET array. The pull-down NFETs are programmatically enabled by a pull-down calibration word pd [5:0], and a pulldown signal to drive the I/O output pad low. The FET arrays are sized such that they exhibit conductance values corresponding to their binary weighted bit position in their respective calibration word pu_n[n:0] or pd[n:0]. Each FET has a conductance value about equal to 2bit positionG. Thus, if bit 0 of the calibration word controls a FET with conductance G, bit 1 of the calibration word controls a FET with a conductance 2 G, bit 2 of the calibration word controls a FET with a conductance 4 G, and so on.
In effect, as the calibration word binary count increments, more resistors are added in parallel in the driver FET array, and reflected in the output impedance response. The construction of the '750 patent flattening circuit requires separate and independent calibration words for each of the pull-up PFET and pull-down NFET arrays. For that matter, due to the non-linear nature of the FET array operation at the time of switching, the output impedance over the different stages of the switching period can still vary undesirably.
Included in the pull-up PFET array is an NFET, and included in the pull-down NFET array is a PFET. Including the complementary NFET with the pull-up PFETs, and the complementary PFET with the pull-down NFETs enables the output driver to supply more current in the initial stages of voltage transitions in attempt to better control the voltage to current ratio and therefore the output signal integrity at switching. Supplying more current through the complementary NFET results in a flatter overall output resistance response during the voltage transition. For example, during a low-to-high transition, the pull-up NFET is conducting. As the output voltage Vo approaches VDD-Vt from 0V, the pull-up NFET enters the cut-off region. The pull-up NFET is cutoff where (VDD−Vt)≦V0≦VDD, and the pull-up PFET array then determines the driver output impedance. The pull-down PFET behaves in a similar fashion during a high-to-low transition.